BITM Digital Logic
Digital Logic
Subject Code: ITM151
Course Title: Digital Logic
Course No: ITM151
Nature of Course: Theory & Practical
Full Marks: 60
Pass Marks: 30
Credit Hours: 3
Course Description
Course Objective
Course Contents
| Course Contents | Teaching Methodology | Teaching Hours |
|---|---|---|
| Unit 1: Introduction (6 Hrs.) | ||
| Digital versus analog signals | Lecture/Lab | |
| Digital integrated circuits (Advantage, Characteristics and Level of Integration) | ||
| Digital system applications | ||
| Digital codes and conversions | ||
| Decimal, binary, octal and hexadecimal codes | ||
| BCD code | ||
| Excess-3 code | ||
| Gray code | ||
| Alphanumeric codes: ASCII code and EBCDIC code | ||
| Binary addition and subtraction | ||
| 1’s complement and 2’s complement | ||
| Signed number representation | ||
| Unit 2: Logic Gates (3 Hrs.) | ||
| Basic gates, Derived gates and Universal gates (NAND, NOR) and their equivalents | Lecture/Lab | |
| Realization of different gates using Universal gates | ||
| Applications of logic gates | ||
| Unit 3: Boolean Algebra and Logic Simplification (8 Hrs.) | ||
| Boolean algebra and its laws | Lecture/Lab | |
| Demorgan’s Theorem | ||
| Simplification of Boolean expressions | ||
| Minterms and maxterms | ||
| Sum-of-product (SOP) and product-of-sum (POS) methods | ||
| Truth tables and Karnaugh map (Up to Four variables) | ||
| Don’t care conditions | ||
| Boolean Function simplification using Quine-McCluskey Method/Tabulation Method | ||
| Unit 4: Combinational Logic Circuits (12 Hrs.) | ||
| Design procedures | Lecture/Lab | |
| Half-adder and full-adder design | ||
| Half-subtractor and full-subtractor design | ||
| Binary adder design | ||
| BCD adder design | ||
| Encoder designs | ||
| Decoder designs | ||
| Multiplexers design | ||
| Boolean function implementation using multiplexer | ||
| Demultiplexer design | ||
| Seven-segment decoder | ||
| Magnitude comparators | ||
| Code Converter | ||
| Programmable Logic Devices (PLA and PAL design) | ||
| Unit 5: Sequential Logic Circuits (6 Hrs.) | ||
| Latches and flip-flops: SR, D, T and JK | Lecture/Lab | |
| Characteristics Table | ||
| Excitation tables and characteristic equations of all flip flops | ||
| Master-slave flip-flops | ||
| Flip-flop applications | ||
| Unit 6: Registers and Counters (10 Hrs.) | ||
| Register | Lecture/Lab | |
| Shift Register (SISO, SIPO, PISO, PIPO and Bidirectional Registers) | ||
| Data transfer timing diagrams | ||
| Asynchronous counters (Up, Down, Mod-N and UP/Down asynchronous counters) | ||
| Synchronous counters (Up, down, Mod-N, UP/Down synchronous counters) | ||
| Shift Register Counter | ||
| Register and counter applications | ||
| Unit 7: Sequential Machine Designs (3 Hrs.) | ||
| Sequential Machine design procedures: state diagram (introduction and example only) | Lecture/Lab | |
| Transition/ State tables | ||
| Reduction of Redundant states | ||
| binary assignment tables | ||
| Excitation Table and output table | ||
| derivation of flip-flop input and Circuit output function, design of a circuit diagram |
Text Books
1. Floyd, T. L. (2015). Digital fundamentals. Pearson Education.
2. Mano, M. M. (1995). Digital logic and computer design (Latest Edition). Prentice Hall.
3. Leach, D. P., Malvino, A. P., & Saha, G. (2012). Digital principles and applications (8th ed.). Tata McGraw-Hill Education.
Lab Works
Students are required to complete hands-on circuit construction and verification exercises for each unit. The following practical tasks are prescribed (45 Practical Hours):
Lab 1: Verify the truth tables of basic gates (AND, OR, NOT), universal gates (NAND, NOR), and exclusive gates (XOR, XNOR) using ICs on a breadboard or Digital Circuit Trainer Board
Lab 2: Demonstrate De’Morgan’s theorem experimentally using NAND and NOR gates; verify equivalent circuit implementations using ICs on a breadboard or Digital Circuit Trainer Board
Lab 3: Design and construct half-adder, full-adder, half-subtractor, and full-subtractor using ICs on a breadboard or Digital Circuit Trainer Board
Lab 4: Design and construct encoder (4-to-2, 8-to-3) and decoder (2-to-4, 3-to-8, BCD decoder) and verify their operations using ICs on a breadboard or Digital Circuit Trainer Board
Lab 5: Design and construct multiplexers (4-to-1, 8-to-1) and demultiplexer (1-to-4, 1-to-8) circuits using ICs on a breadboard or Digital Circuit Trainer Board
Lab 6: Design and construct any three-code converter using ICs on a breadboard or Digital Circuit Trainer Board
Lab 7: Build and analyze SR latch, gated SR latch, and T flip-flop circuits; observe triggering behavior using ICs on a breadboard or Digital Circuit Trainer Board or available simulator tools.
Lab 8: Construct D flip-flop and JK flip-flop circuits; implement a master-slave JK flip-flop and observe its behavior using ICs on a breadboard or Digital Circuit Trainer Board or available simulator tools.
Lab 9: Design and observe SISO, SIPO shift register using ICs on a breadboard or Digital Circuit Trainer Board or available simulator tools.
Lab 10: Design and observe PISO, and PIPO shift register using ICs on a breadboard or Digital Circuit Trainer Board or available simulator tools.
Lab 11: Design and observe bidirectional shift register configurations using ICs on a breadboard or Digital Circuit Trainer Board or available simulator tools.
Lab 12: Design and test a 3-bit and a 4-bit asynchronous (ripple) counter; observe modulus and up/down counting behavior on LEDs using ICs on a breadboard or Digital Circuit Trainer Board or available simulator tools.
Lab 13: Design and test a 3-bit and a 4-bit synchronous counter; observe modulus and up/down counting behavior on LEDs using ICs on a breadboard or Digital Circuit Trainer Board or available simulator tools.
