BIT Microprocessor and Computer Architecture

Definition of Microprocessor Components: Registers, ALU, Control and Timing, System Buses (Address, Data, Control), Microprocessor System with Bus Organization. SAP-1 Architecture: Block Diagram, and Function of each Block. SAP-1 Instructions: LDA, ADD, SUB, OUT, HLT. Fetch and Execution Cycle of SAP-1 Instructions with Timing Diagram Fetch Cycle: Address State, Increment State, Memory State; Execution Cycle of LDA only. SAP-2 Architecture: Block Diagram and Functions of each Block, Architectural Differences with SAP-1 Bidirectional Registers; Flags.

Functional Block Diagram, Pin Configuration, Description of each Block: Registers, Flag (Description of each Flag), Data and Address Bus including Bidirectional Address/Data Bus, Timing and Control Unit, Interrupts (Introduction Only), Instructions: Op-Code and Operands Addressing Modes, Instructions and Data Flow. 8085 Instructions: Data Transfer MOV, IN, OUT, STA, LDA, LXI, LDAX, STAX, XCHG. Arithmetic and Logic ADD, SUB, INR, DCR, AND, OR, XOR, CMP, RLC, RRC, RAL, RAR. Branching JMP, JNZ, JZ, JNC, JC. Basic Assembly Language Programming using 8085 Instruction Sets: Addition, Subtraction, Multiplication and Division, Simple Sequence Programs, Array Searching and Sorting using Branching and Looping, Conversion (BCD to ASCII).

Arithmetic Micro Operations: Addition, Subtraction, Increment, Decrement, Hardware Implementation. Logic Micro Operations: AND, OR, NOT, NAND, NOR, XOR, Selective Set, Set(preset), Selective Complement(toggling), Insert, Hardware Implementation. Shift Micro Operations: Logical, Circular and Arithmetic, Arithmetic Logic Shift Unit.

Control Unit of Basic Computer and Timing Signal (Hardwired Vs. Microprogrammed). Micro-operation, Micro-instruction, Micro-program: Symbolic and Binary Micro-program (FETCH and ADD). Architecture of Basic Computer: Register organization, Common Bus System Instruction Format, Register Stack and Memory Stack. Data Transfer operations and Manipulation (Arithmetic, Logical, Shift). Introduction to RISC and CISC (Basic Differences).

Signed number Representation: Signed Magnitude, 1's Complement and 2's Complement Form. Addition and Subtraction (with Numerical Example), Addition and Subtraction with Signed Magnitude Data, Hardware implementation, Hardware Algorithm, Addition and Subtraction with Signed 2's Complemented Data. Multiplication Algorithm: Hardware Implementation for Signed Magnitude Data, Booth Multiplication Algorithm (with Numerical Example). Division Algorithm: Hardware Implementation for Signed Magnitude Data, Hardware Algorithm (Restoring Only).

Introduction to Peripheral Devices, I/O interface-I/O bus and Interface Modules, Isolated versus Memory Mapped I/O. Direct Memory Access (DMA): Introduction, Basic DMA Procedures (DMA controller only). I/O Processor, Data Communication Processor: Character Oriented Protocol and Bit Oriented Protocol.

Hierarchy of Memory System. Primary Memory: RAM and ROM, Memory Address Map with examples of Address Decoding. Secondary Memory: Structure of Magnetic Disk. Virtual Memory: Concept, Address Mapping with Pages, Basic Idea about Page Fault and Page Replacement. Memory Management Hardware: Segmented Page Mapping (Introduction), Memory Protection.

Concept of Pipelining and Flynn's Classification, Pipelining Example with Speed Up Ratio. Arithmetic Pipeline, Pipeline for Floating-point Addition and Subtraction. Instruction Pipeline: Four Segment Instruction Pipeline. Data Dependency, Handling of Branch Instruction.