BIT Digital Logic
bitsemester 1
Digital Logic
Subject Code: BIT103
Course Title: Digital Logic
Course No: BIT103
Nature of Course: Theory & Practical
Full Marks: 100
Pass Marks: 40
Credit Hours: 3
Course Description
This course familiarizes students with Number System, Digital Design Fundamentals, Understand and Design Functions of Combinational Logic, Sequential Logic (Counters, Registers and Finite State Machine), Memories, Programmable Logic Devices Integrated Circuit Technologies.
Course Objective
To provide the concepts used in the design and analysis of digital systems and introduces the principles of digital computer organization and design.
Course Contents
| Course Contents | Teaching Methodology | Teaching Hours |
|---|---|---|
| Unit 1: Number Systems, Operations and Codes (6 Hrs.) | ||
| History of Number System, Introduction to Number System (Positional and Non positional), Decimal, Binary, Octal, Hexadecimal Number Systems | Lecture | 1 |
| Conversion from one number system to another (Binary, Octal, Hex to Decimal; Decimal to Binary, Octal and Hex; Binary to Octal, Octal to Binary, Binary to Hex, Hex to binary) | 2 | |
| Compliment of Number Systems (r's complement and r-1's compliment with r as 2 and 10) | 1 | |
| Addition and Subtraction of Binary Numbers, Binary Codes (Absolute, Gray Code, weighted binary code, BCD, ASCII, Unicode) and Error Detection Codes | 2 | |
| Unit 2: Digital Design Fundamentals and Boolean algebra (8 Hrs.) | ||
| Digital and Analog Signals (Definition, example and difference between them) | Lecture/Lab | 1 |
| Logic Operations (Definition and Truth Table of AND, OR, NOT) | 1 | |
| Introduction to the System Concept, Logic Gates (Basic Gates, Derived Gates, Universal Gates) | 2 | |
| Logic Function and Boolean Algebra (characteristics, laws, simplifications using laws, principle of duality) | 4 | |
| Unit 3: Simplification of Boolean Functions (5 Hrs.) | ||
| K-map, Two and Three variable maps, Four variable maps, product of sum simplification | Lecture | 2 |
| NAND and NOR implementation, Don't Care conditions | 2 | |
| Unit 4: Combinational Logic (7 Hrs.) | ||
| Adders and Subtractors (Half and full binary adder and subtractor), Parallel Binary Adders | 2 | |
| Multiplexers and Demultiplexers | 2 | |
| Encoders and Decoders, Seven segment decoder | 2 | |
| Code Converters, Magnitude comparator (2 bit and 4 bit) | 1 | |
| Unit 5: Sequential Logic (4 Hrs.) | ||
| Latches and Flip-Flops (RS, JK, D, T, Master-Slave), Edge-Triggered Flip-Flops | Lecture/Lab | 2 |
| Flip-Flop Operating Characteristics, Flip-Flop Applications | 2 | |
| Unit 6: Counters, Registers and Memory (9 Hrs.) | ||
| Asynchronous Counters, Synchronous Counters, Up/Down Counters, Counter Applications | Lecture/Lab | 3 |
| Basic Shift Register Operations, Shift Register Types, Bidirectional Shift Registers, Shift Register Counters | 3 | |
| Basic Memory Operations and memory types (ROM, PLA, PAL) | 3 | |
| Unit 7: Processor Logic Design (6 Hrs.) | ||
| Processor Organization, Arithmetic Logic Unit, Design of Arithmetic Circuit, Design of Logic Circuit, Design of Arithmetic Logic Unit (one bit ALU design only) Status Register, Design of Shifter (4 bit combinational logic shifter) | Lecture/Lab | 6 |
Text Books
Mano M.M., Digital logic and Computer Design, Pearson Education
Reference Books
- Mano M.M. and Ciletti M. M, Digital Design, 4th edition
- Brown S. and Vranesic Z., Fundamentals of Digital Logic with VHDL Design, 3rd edition, McGraw Hill
- Rafiquzzaman M., Fundamentals of Digital Logic and Microcomputer Design, 5th edition, John Wiley & Sons, Inc.
- Holdsworth B. and Woods C., Digital Logic Design, 4th edition
- Mano M. M, Kime C. R, Logic and Computer Design Fundamentals, 2nd edition
Lab Works
The following lab activities are carried out using Digital Logic Kit, Bread board and Simulator.
- Familiarization with Logic Gates
- DeMorgan's law and its familiarization with NAND and NOR gates
- Encoder, Decoder, Multiplexer and Demultiplexer, Seven segment display
- Familiarization with Binary Addition and Subtraction
- To realize a. Half Adder and Full Adder and Half Subtractor and Full Subtractor by using Basic gates and NAND gates
- Implementation of true complement generator
- Implementation of RS and T type flip flops
- Implementation of D and JK type flip flops
- Ripple Counter, Synchronous counter
- Conversion of parallel data into serial format
- Generation of timing signal for sequential system
- Familiarization with PLAs and PLDs