BCA Microprocessor and Computer Architecture

Definition of Microprocessor Components: Registers, ALU, Control and Timing, System Buses (Address, Data, Control), Microprocessor System with Bus Organization, Application of MP.

Functional Block Diagram, Pin Configuration, Description of each Block: Registers, Flag (Description of each Flag), Multiplex Address data bus (Ad0-Ad7), Timing and Control Unit, Interrupts (Introduction Only), Addressing Modes, Instruction cycle, Machine cycle (Opcode, fetch, memory read, memory write) and T states, Timing diagram of MOV, LDA, STA, MVI, 8085 Instruction Set, Data Transfer: MOV, MVI, STA, LDA, LXI, LDAX, STAX, XCHG, Arithmetic: ADD, ADI, ADC, SUB, SUI, SBB, INR, DCR, INX, DCX, Logic: ANA, ANI, ORA, ORI, XRA, XRI, CMA, CMP, Branching: JMP, JNZ, JZ, JNC, JC, Basic Assembly Language Programming using 8085 Instruction Sets, Addition (8 and 16 bit), Subtraction (8 and 16 bit), Multiplication (8 bit) and Division (8 bit), Simple Sequence Program, Array Searching using branching and looping.

Logical block diagram and components, Bus interface unit and Execution Unit, flag, pipeline concept, Memory Segmentation, Segmentation register.

Stored Program Organization, Computer Registers, Common bus system, Instruction set, Timing and Control-Instruction Cycle, Micro-Operation, Arithmetic Micro Operations: Addition, Subtraction, Increment, Decrement, Logic Micro Operations: AND, OR, NOT, NAND, NOR, XOR, Shift Micro Operations: Logical, Circular and Arithmetic.

Hardwired vs micro program CU, Control Memory, Address Sequencing, Micro-operation, Micro instruction, Micro Instruction Format, Micro-program: Symbolic and Binary Micro-program (FETCH)

Introduction, General Register Organization, Stack Organization, Instruction Formats: 3, 2, 1, 0 address Instruction, RISC and CISC architecture.

Addition and Subtraction with signed magnitude data, Addition and Subtraction with signed 2's complement data, Booth Multiplication.

Introduction to Peripheral Devices, I/O interface-I/O bus and Interface Modules, Isolated versus Memory Mapped I/O, Interrupt, Direct Memory Access (DMA): Introduction, Basic DMA Procedures (DMA controller only), Hierarchy of Memory System, Primary Memory: RAM and ROM, Memory Address Map with examples of Address Decoding, Secondary Memory: Structure of Magnetic Disk, Cache Memory.

Concept of Pipelining and Flynn's Classification, Pipelining Example with Speed Up Ratio, Arithmetic Pipeline, Pipeline for Floating-point Addition and Subtraction, Instruction Pipeline: Four Segment Instruction Pipeline, Data Dependency, Handling of Branch Instruction, pipeline hazard and its solution.